Static timing analysis (STA) is a key step in the design of high speed very large scale integrated (VLSI) circuits. STA is used to verify that a VLSI chip performs correctly at the required frequency before it is released to manufacturing. STA typically consists of the following main steps: 1) Delay calculation, which involves modeling and calculating path delays for the gates and interconnects contained in the design, 2) Propagation of arrival, required arrival times and slews, and 3) Slack calculation for the paths in the design.
Referring to FIG. 1a, there is shown a conventional overall delay from input pin A of the CMOS inverter 108 to the input pin C of the NAND2 gate 107. This delay is obtained by adding the gate delay from input pin A to the output pin B of CMOS inverter 108 and the interconnect propagation delay from output pin B of the inverter 108 to the input pin C of the NAND2 gate 107, as in EQ. 1. This overall delay is also defined as the stage delay 110, and represents the propagation delay between the voltage waveforms 109 and 104, for a given voltage threshold crossing point of the waveforms.DelayAC=DelayAB+DelayBC  EQ. 1
The voltage waveform 109 at the sink of the interconnect network 105 is a function of the voltage waveform 103 at the input terminal of the interconnect network, the interconnect parasitics 105 and the input capacitance 106 of each gate 107 at the sink terminal(s) of the interconnect network. The interconnect delay and output slew are calculated by fitting a ramp or a piece-wise-linear waveform to the voltage waveform 103 at the input terminal of the interconnect network, and subsequently convolving it with the transfer function of the interconnect load. Various Model Order Reduction (MOR) techniques such as Asymptotic Waveform Evaluation (AWE) and Passive Reduced-order Interconnect Macromodeling Algorithm (PRIMA) have been proposed for accurate interconnect timing analysis. These techniques reduce the complexity of a large-scale interconnect network to a smaller one while preserving (to the possible extent) their input-output behavior. Alternatively, a large-scale interconnect network is approximated (reduced) to a smaller interconnect network so that when the same input signal is applied to both, the output response of the original and the approximated (reduced) network closely match each other. Higher order reduced models offer increased accuracy at the cost of increasing the complexity of the analysis. For instance, a first reduced order model can be analyzed very fast, but it may introduce significant errors in the input-output behavior of the system. Consequently, a trade-off between accuracy and speed for determining the order of the reduced model is performed.
The voltage waveform 103 at the output of the gate 108 is a function of different parameters that includes the voltage waveform 104 at the input terminal of the gate (which is propagated from the previous stages of the design), the interconnect parasitics 105, the input pin capacitance 106 of each gate 107 at the sink of the interconnect, and the characteristics of the primitive gate 108. Given the input voltage waveform 104, the gate timing library, the load parasitics 105, and the input pin capacitance 106 of each gate connected to the interconnect sink terminal(s), the gate timing analysis process calculates the gate output voltage waveform 103 and/or its characteristics with respect to the characteristics of the gate input voltage waveform 104 (e.g., the gate propagation delay and output slew).
Various gate modeling techniques have been employed for gate timing analysis. Three well-known techniques are based on: (1) using delay and slew polynomial equations which are characterized as a function of input slew and output capacitive load; (2) using delay and slew tables which are characterized as a function of the input slew and output capacitive load; and (3) using current source models where the output voltage/current is characterized as a function of input slew and output load, while the output voltage/current waveforms are tabulated. Each of these gate models are also characterized as a function of manufacturing process parameters (e.g. Leff, doping concentration), and the environmental parameters (e.g., voltage, temperature).
The aforementioned models are all characterized as a function of input slew and output capacitive load. Given some slew at an input terminal of a gate and an approximated capacitive load at its output terminal, the gate propagation delay is obtained directly from the gate delay model. However, in very deep sub-micron (VDSM) technologies, the effect of interconnect resistive parasitics is significant and render approximating the interconnect load by a lumped capacitance susceptible to error. Using the sum of all the load capacitances as the capacitive load is a simple, albeit inaccurate approximation. A more accurate approximation for an nth order load seen by the gate (i.e., a load having n distributed capacitances to ground) is to use a reduced order model. As an example, for the case of resistive capacitive interconnects, the load can be approximated by a second order RC-π model. Equating the first, second, and third moments of the admittance of the real load with the first, second, and third moments, respectively of the RC-π load, the parameters Cn, Rπ, and Cf of the RC-π model, as shown in FIG. 1 (b) are obtained. The RC-π parameters are therefore functions of the input pin capacitance of each gate in the fan-out of the primitive gate. An “effective capacitance” technique is proposed, whereby the reduced order model load (e.g. the RC-π load) is approximated by an equivalent capacitance. The aforementioned models are then employed to obtain the gate delay and output slew, given the slew 115, at the input pin of the gate and the reduced order RC-π load 118.
Conventional Static Timing Analysis (STA) propagates signal timing information from the circuit primary inputs through gates and interconnects to calculate the earliest/latest signal arrival times/voltage waveforms at the circuit primary outputs. A typical conventional STA has a linear run-time complexity with respect to the number of the gates in the design. During the interconnect delay analysis, the input pin impedance of pins connected to the sink terminal(s) of the interconnect network are represented by fixed pin capacitance values.
The technology scaling to sub-90 nm geometry introduces new challenges that need to be addressed during timing analysis of VLSI circuits. Many model assumptions which have been made in 90+ nm nodes are no longer valid. Constant pin capacitance models no longer accurately describe the pin's loading contribution to the total load as seen by the source terminal of the interconnect network. Generally speaking, the gate input pin impedance may vary during the voltage transition at the input pin of the CMOS gate. In addition, its value is dependent on the loading condition at the output pin of that CMOS gate. Present industry standard gate current-source models offer two ways of modeling gate input pin capacitances: 1) the Effective Current Source Model (ECSM) format which models the input pin capacitance as a function of Slew and Output capacitive Load, and 2) the Composite Current Source (CCS) format that employs a two-piece pin capacitance model for each input slew/output capacitance combination. Both these models are table-based representations.
FIG. 2 shows the Slew and Output capacitive Load Dependent Pin Capacitances (referred hereinafter as SOLDPC) for ECSM and CCS. As shown in FIG. 2, the pin-capacitance definition in ECSM consists of a two-dimensional table. During characterization, a ramp input slew and output capacitive load is applied to the CMOS gate, and the effective input pin capacitance of the gate is calculated as the amount of charge that needs to be injected to the input pin of the driver divided by the supply voltage (Vdd) as follows:
                              C          pin                =                                            ∫                                                                    t                    1                                    ⁢                                      V                    ⁡                                          (                                              t                        1                                            )                                                                      =                0                                                                                  t                    2                                    ⁢                                      V                    ⁡                                          (                                              t                        2                                            )                                                                      =                0                                      ⁢                                          ⅈ                ⁡                                  (                  t                  )                                            ⁢                                                          ⁢                              ⅆ                t                                              Vdd                                    EQ        .                                  ⁢        2            
CCS uses a similar characterization method to calculate a two-piece input pin capacitance for every combination of the input slew and output load as follows:
                                          C            1                    =                                                    ∫                                                                            t                      1                                        ⁢                                          V                      ⁡                                              (                                                  t                          1                                                )                                                                              =                  0                                                                                            t                      2                                        ⁢                                          V                      ⁡                                              (                                                  t                          2                                                )                                                                              =                                      Vdd                    /                    2                                                              ⁢                                                ⅈ                  ⁡                                      (                    t                    )                                                  ⁢                                                                  ⁢                                  ⅆ                  t                                                                    Vdd              /              2                                      ,                                  ⁢                              C            2                    =                                                    ∫                                                                            t                      2                                        ⁢                                          V                      ⁡                                              (                                                  t                          2                                                )                                                                              =                                      Vdd                    /                    2                                                                                                              t                      3                                        ⁢                                          V                      ⁡                                              (                                                  t                          3                                                )                                                                              =                  Vdd                                            ⁢                                                ⅈ                  ⁡                                      (                    t                    )                                                  ⁢                                                                  ⁢                                  ⅆ                  t                                                                    Vdd              /              2                                                          EQ        .                                  ⁢        3            
C1 represents the pin capacitance before the CMOS gate switches, while C2 represents the pin capacitance after the gate switches. SOLDPC modeling may be generalized to an n-piece pin capacitance model for each slew/output load combination.